Method for stabilizing or offsetting voltage in an integrated circuit

ABSTRACT

A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

[0001] This application is a Divisional of U.S. application Ser. No.09/940,328, filed Aug. 27, 2001, which is a Divisional of U.S.application Ser. No. 09/838,526, filed Apr. 19, 2001, now U.S. Pat. No.6,410,955.

FIELD OF THE INVENTION

[0002] The present invention relates generally to electronic circuits,and more particularly to a capacitor for use in integrated circuits.

BACKGROUND INFORMATION

[0003] There is a continuing demand for integrated circuits to performmore functions or operations in shorter periods of time. This typicallyrequires additional components to perform the additional functions,store more data and operate more efficiently. At the same time packagingrequirements are decreasing. Consumers want smaller, lighter weightproducts that do more and are more mobile or portable. Accordingly,circuit designers are challenged to provide more components or greatercapacity per unit of area on a semiconductor die. Most electroniccircuits include basic electrical components such as transistors,resistors, inductors, capacitors and the like. Capacitors are onecomponent that can occupy a lot of area on a semiconductor die dependingupon the size of the capacitor. Capacitors are typically made bydepositing a first metal plate, depositing a layer of insulationmaterial over the first metal plate and then depositing a second metalplate over the layer of insulation material and parallel to the firstmetal plate. The size of the capacitance will be a function of thesurface area of the two facing parallel plates and other parameters suchas the dielectric constant of the insulation material and the spacingbetween the plates. Accordingly, one primary means of increasing thecapacitance, is to increase the size of each of the parallel plates butthis will consume more area on the semiconductor die.

[0004] Additionally, in some circuits it may be desirable for thecapacitor to be independent of voltage and frequency applied across thecapacitor once it is charged to a predetermined level. For example, acapacitor may be connected to the non-inverting input of an operationalamplifier to reduce or cancel the offset voltage inherent in theoperational amplifier. The capacitor may be pre-charged to the oppositepolarity of the offset voltage of the amplifier so that the offsetvoltage is canceled during normal operation of the amplifier. When aninput voltage signal is applied to the input of the operationalamplifier, the output voltage signal will be stable and uninfluenced bythe offset voltage if the capacitor is voltage and frequencyindependent.

[0005] Accordingly, for the reason stated above, and for other reasonsthat will become apparent upon reading and understanding the presentspecification, there is a need for a capacitor that maximizes the amountof capacitance per unit of area of a semiconductor die and that isindependent of voltage and frequency.

SUMMARY OF THE INVENTION

[0006] In accordance with the present invention, a capacitor includes alayer of conductive material formed on a substrate or semiconductor die.The layer of conductive material includes a first portion and a secondportion. The first and second portions are arranged in a predeterminedpattern relative to one another to provide a maximum amount ofcapacitance per unit of area on the substrate or semiconductor die.

[0007] In accordance with one embodiment of the present invention, thefirst portion and the second portion of the layer of conductive materialeach have a substantially comb-like structure with a plurality of teeth.The teeth of the first portion and the teeth of the second portion areinterleaved and each tooth includes a pair of sidewalls. Each sidewall,except an outside sidewall of an end tooth, faces a sidewall of a toothof the other portion to provide a maximum of juxtaposed surface area.

[0008] In accordance with another embodiment of the present invention,an integrated circuit includes an amplifier formed on a substrate orsemiconductor die and a capacitor formed on the substrate and connectedto an input of the amplifier. The capacitor includes a firstsubstantially comb-like structure of conductive material with aplurality of teeth and a second substantially comb-like structure ofconductive material also with a plurality of teeth. The teeth of thesecond substantially comb-like structure are interleaved with the teethof the first substantially comb-like structure and each tooth of thefirst and second comb-like structures have a pair of sidewalls. Eachsidewall has a selected surface area and each of the teeth of the firstand second comb-like structures are separated by a gap of a chosen widthto provide a predetermined capacitance.

[0009] In accordance with another embodiment of the present invention, amemory system includes an array of memory elements. Each memory elementis connected by one of plurality of row lines and by one of a pluralityof column lines. An amplifier is connected to at least one of each ofthe plurality of column lines or each of the plurality of row lines. Acapacitor is connected to an input of each amplifier to cancel theoffset voltage of the amplifier. The capacitor includes a layer ofconductive material having a first portion and a second portion. Thefirst portion and the second portion are arranged in a predeterminedpattern relative to one another to provide a maximum amount ofcapacitance per given area of the substrate or semiconductor die.

[0010] In accordance with a further embodiment of the present invention,a electronic system includes a processor and a memory device coupled tothe processor. The memory device includes an array of memory elementsand each memory element is connected by one of a plurality of row linesand by one of a plurality of column lines. An amplifier is connected toat least one of each of the plurality of row lines or to each of theplurality of column lines. A capacitor is connected to an input of eachamplifier to cancel the offset voltage. Each capacitor includes a layerof conductive material divided into a first portion and a secondportion. The first and second portions are arranged in a predeterminedpattern relative to one another to provide a maximum amount ofcapacitance per given area of a substrate or semiconductor die.

[0011] In accordance with a further embodiment of the present invention,a method for making a capacitor includes depositing at least one layerof conductive material on a substrate; removing material from the layerof conductive material to form a first and second portion arranged in apredetermined pattern relative to one another to provide a maximumamount of capacitance per area of the substrate or wafer.

[0012] In accordance with another embodiment of the present invention, amethod for correcting for offset voltage in an amplifier includes:connecting an output of the amplifier to an inverting input of theamplifier; connecting a capacitor between the inverting input and apositive or non-inverting input of the amplifier, wherein the capacitorcomprises a layer of conductive material including at least a firstportion and a second portion and wherein the first portion and thesecond portion are arranged in a predetermined pattern relative to oneanother to provide a maximum capacitance per area; and connecting thepositive input of the amplifier to ground to cause the capacitor tocharge to the offset voltage.

[0013] In accordance with a further embodiment of the present invention,a method for applying a stable voltage to a column or a row line of amemory device includes forming an amplifier and connecting an output ofthe amplifier to one of the row line or the column line; forming acapacitor connected to an input of the amplifier, wherein the capacitoris formed by depositing at least one layer of conductive material andremoving material from the at least one layer of conductive material toform a first portion and a second portion that are arranged in apredetermined pattern relative to one another to provide a maximumcapacitance per area of a semiconductor wafer or die; and formingcircuitry to charge the capacitor to an opposite polarity of the offsetvoltage to nullify the offset voltage of the amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the drawings like reference numerals describe substantiallysimilar components throughout the several views. Like numerals havingdifferent letter suffixes represent different instances of substantiallysimilar components.

[0015]FIG. 1 is a side elevation view of a capacitor in accordance withone embodiment of the present invention.

[0016]FIG. 2 is a cross-section view of the capacitor of FIG. 1 takenalong lines 2-2.

[0017]FIG. 3 is a partial side elevation view of a capacitor inaccordance with another embodiment of the present invention.

[0018]FIG. 4 is a side elevation view of a capacitor in accordance witha further embodiment of the present invention.

[0019]FIG. 5 is a schematic diagram of an offset or operationalamplifier and offset capacitor in accordance with an embodiment of thepresent invention.

[0020]FIG. 6 is schematic diagram of a portion of a memory device orsystem including an operational amplifier and offset capacitor inaccordance with an embodiment of the present invention.

[0021]FIG. 7 is a top view of a wafer or substrate containingsemiconductor dies in accordance with an embodiment of the presentinvention.

[0022]FIG. 8 is a block diagram of an exemplary circuit module inaccordance with an embodiment of the present invention.

[0023]FIG. 9 is a block diagram of an exemplary memory module inaccordance with an embodiment of the present invention.

[0024]FIG. 10 is a block diagram of an exemplary electronic system inaccordance with the present invention.

[0025]FIG. 11 is a block diagram of an exemplary memory system inaccordance with the present invention.

[0026]FIG. 12 is a block diagram of an exemplary computer system inaccordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] In the following detailed description of the preferredembodiments, reference is made to the accompanying drawings which form apart hereof, and in which is shown by way of illustration specificembodiments in which the invention may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that process or mechanical changes maybe made without departing from the scope of the present invention. Theterms wafer and substrate used in the following description include anybase semiconductor structure. Both are to be understood as includingsilicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI)technology, thin film transistor (TFT) technology, doped and undopedsemiconductors, epitaxial layers of a silicon supported by a basesemiconductor, as well as other semiconductor support structures wellknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been utilized to form regions/junctions in the basesemiconductor structure. The following detailed description is,therefore, not to be taken in a limiting sense, and the scope of thepresent invention is defined only by the appended claims.

[0028] Referring to FIGS. 1 and 2, FIG. 1 is a side elevation of acapacitor 100 in accordance with the present invention. The capacitor100 may be formed on a substrate 102 or semiconductor wafer. A layer 104of conductive material is deposited on the substrate 102 by chemicalvapor deposition (CVD) or similar techniques to a selected height “H.”The conductive layer 104 may be tungsten. The conductive layer 104 isthen etched by photo resistive techniques, mechanical etching or thelike to form a first portion 106 and a second portion 108 arranged in apredetermined pattern relative to one another to provide a maximumamount of juxtaposed surface area between the first and second portions106 and 108 and accordingly a maximum amount of capacitance per unit ofarea of the substrate 102 or semiconductor wafer on which the capacitor100 is formed. In accordance with one embodiment of the invention, thepredetermined pattern of the first portion 106 and the second portion108 may be substantially comb-like structures as shown in FIG. 2. Eachof the first and second portions 106 and 108 include a plurality ofteeth 110. Each tooth 110 has a sidewall 112 with a selected height “H”corresponding to the height of the conductive layer 104 and length “L”to provide a selected surface area facing a juxtaposed surface area ofthe other portion 106 or 108. The capacitor 100 is then formed by thejuxtaposed sidewalls 112 of the teeth 110 of the first and secondportions 106 and 108 corresponding to parallel plates of a capacitor asillustrated by the standard capacitor symbols 114 shown by broken linesbetween the sidewalls 112 in FIGS. 1 and 2. The interleaved teeth 110 ofthe comb-like structures of first and second portions 106 and 108provide a maximum amount of capacitance per unit of area of thesubstrate 102.

[0029] In the predetermined pattern, the first and second portions 106and 108 are separated by a substantially serpentine-shaped gap of aselected width “W.” A layer of insulation material 116 is deposited overand between the first and second portions 106 and 108. The value oramount of the capacitance formed by the first and second portions 106and 108 will be a function of the surface area of the juxtaposedsidewalls 112, the width W of the gap between the first and secondportions 106 and 108 and the dielectric constant of the insulation layer116. Accordingly, the value or amount of the capacitance may bepredetermined by selecting the length L and height H of the juxtaposedsidewalls 112 to provide a selected surface area, choosing the width ofthe gap W and selecting the dielectric constant of the insulation layer116.

[0030] While the predetermined pattern of the first and second portions106 and 108 have been described an a substantially comb-like structure,it should be noted that other patterns may be used as well to provide apredetermined or desired capacitance. Interconnected strips of materialof a selected height and width that are interleaved with otherinterconnected strips of material may be used to provide the desiredcapacitance value.

[0031] In accordance with one embodiment of the present invention shownin FIG. 1, a reference plate 118 of conductive or semiconductivematerial may be disposed on the insulation layer 116 and over the firstand second portions 106 and 108. The reference plate 118 is electricallyconnected to one of the first or second portions 106 or 108 by at leastone contact or plug 120. The plugs may be formed by creating vias orholes through the insulation layer 116 and then depositing a conductivematerial in the via in contact with the first portion 106 or the secondportion 108. The plugs 120 may be formed from tungsten, copper, aluminumor the like. The reference plate 118 will provide further capacitancebetween itself and the one of the first or second portions 106 or 108that is not electrically connected to the reference plate 118. Thereference plate 118 is then preferably covered by another insulationlayer 119. While the reference plate 118 is shown in FIG. 1 and beingdisposed over the first and second portions 106 and 108, the referenceplate 118 could have also been formed on the substrate 102 first andthen the first and second portions 106 and 108 could have been formedover the reference plate 118.

[0032] In another embodiment of the present invention shown in FIG. 3,the layer of conductive material 104 may include a first layer ofmetalization, semiconductor material or polysilicon 122, a second layerof tungsten 124 disposed over the first layer of metalization 122 and athird layer of metalization, semiconductor material or polysilicon 126or polysilicon disposed over the second layer of tungsten 124. All threelayers 122, 124 and 126 are then etched to form the teeth 110 of thefirst and second portions 106 and 108. The capacitance 100′ is thereforecreated between the sidewalls 112 as illustrated by the capacitorsymbols 114 in broken lines and between the metalization layers 122 and126. The metalizations layers 122 and 126 may be much thinner than thetungsten layer 124.

[0033] In another embodiment of the present invention shown in FIG. 4, acapacitor 100″ is similar to the capacitor 100 in FIGS. 1 and 2 andincludes a first reference plate or layer 302 of conductive orsemiconductive material formed on the substrate 102 or silicon wafer. Alayer of insulation material 316 is disposed over the first referenceplate 302. At least one hole or via 318 is formed in the insulationlayer 316 and contacts or plugs 320 are formed in the vias 318 toelectrically connect the first reference plate 302 to the teeth 110 ofone of the first or second portions 106 or 108. A layer of conductivematerial 104 is deposited on the insulation layer 316 and is etched toform the first portion 106 and the second portion 108. The first andsecond portions 106 and 108 will preferably be formed in a predeterminedpattern to provide the maximum amount of juxtaposed surface area andtherefore the maximum amount of capacitance per unit of area of thesubstrate 102 similar to that described with respect the capacitor 100in FIGS. 1 and 2. Accordingly, the first and second portions 106 and 108may also be comb-like structures similar to those in FIGS. 1 and 2;although other patterns may be used as well to provide a predeterminedcapacitance value. A further layer of insulation material 321 isdeposited over the first and second portions 106 and 108. At least onehole or via 322 is formed through the insulation material 321 exposingwhichever of the first or second portions 106 or 108 that is contactedby the first reference plate 302. A plug or contact 324 of conductivematerial is deposited in the hole 322 in contact with the first orsecond portion 106 or 108. A second reference plate 326 of conductive orsemiconductive material is then deposited on the insulation materiallayer 321 and in contact with the at least one plug 324. Accordingly,the reference plates 302 and 326 form additional capacitance withwhichever of the first and second portions 106 or 108 that is notconnected by the plugs 320 and 324 to the first and second referenceplates 302 and 326. The plugs 320 and 324 may be made from tungsten. Thefirst portion 106 and the second portion 108 may also be made fromtungsten or may be two metalization layers separated by a thicker layerof tungsten similar to the teeth 110 shown in FIG. 3.

[0034] One application of the capacitor 100 is as an offset capacitor100 in an operational amplifier circuit 400 to reduce or cancel theoffset voltage (Vos) of an operational amplifier 402 as shown in FIG. 5.The offset capacitor 100 may be connected to the non-inverting orpositive input of the operational amplifier 402. A first switch 404 isconnected between an output (Vout) of the amplifier 402 and an invertingor negative input of the amplifier 400. A second switch 406 is connectedbetween the inverting input of the amplifier 402 and one side of thecapacitor 100. The other side of the capacitor 100 is connected to thenon-inverting input of the amplifier 402, and a third switch 408 isconnected between the other side of the capacitor 100 at a node 410 andground. Another pair of switches 412 and 414 respectively connect ordisconnect any input signals V− or V+ from the inverting andnon-inverting inputs of the amplifier 402.

[0035] In operation, a timing signal φ₁ may be generated by a controlleror processor (not shown in FIG. 5) to close switches 404, 406 and 408.The capacitor 100 will then be charged to the level of the offsetvoltage Vos but with the opposite polarity of the offset voltage tonullify or cancel the offset voltage during normal operation of theamplifier 402. After a predetermined time delay to fully charge thecapacitor 100 to the offset voltage, switches 404, 406 and 408 areopened or another signal may be generated to open switches 404, 406 and408, and a timing signal φ₂ is generated to connect any input signals tothe operational amplifier 402. The offset capacitor 100 will then cancelthe offset voltage Vos to provide a stable output voltage Vout that isindependent of the input voltage and frequency.

[0036] Referring to FIG. 6, one application of the operational amplifiercircuit 400 of FIG. 5 is to drive the column lines of a magnetic randomaccess memory (MRAM) device or system 500. A simplified schematicdiagram of a portion of an MRAM system 500 is shown in FIG. 6. Theamplifier 402 is preferably connected to a multiplexer 502 and themultiplexer 502 is connected to a plurality of column lines C₀-C_(n). Aplurality of amplifier circuits 400 could be used rather than themultiplexer 502 with an amplifier circuit 400 being connected to eachcolumn line; however, the plurality of amplifier circuits 400 wouldoccupy much more area on a substrate or semiconductor die (not shown inFIG. 6) that is better used for other components such a memory array 504or matrix. The memory array 504 includes a plurality of resistiveelements or memory elements 506. Each memory element 506 is connectedbetween each column line C₀-C_(n) and row line R₀-R_(n). A sensor device508 is connected by leads 510 to each of the row lines to sense thecurrent when a row line is active to retrieve or read information fromthe MRAM system 500. The current in an active row line should be precisefor sensing to function correctly. Accordingly, to provide an accuratecurrent level and proper sensing, the associated column lines must beheld at a stable, constant reference voltage level. A variation of oneor two millivolts could provide erroneous sensing of the row lines.Accordingly, the reference output voltage Vout from the amplifiercircuit 400 that is applied to the column lines must be very stable andnot influenced by the offset voltage of the operational amplifier 402.The capacitor 100 must therefore accurately nullify the offset voltageand not be influenced or vary as a result of voltage or frequencychanges associated with the input signals; in other words, the capacitor100 should be independent of voltage and frequency.

[0037] The present invention provides a relatively large bipolarcapacitor in terms of the number of microfarads per unit of die areacompared to other uses of capacitors in memory circuits which havecapacitances on the order of nanofarads or femtofarads per unit of area.As described above, the large capacitance values are required in theMRAM amplifier circuit to provide the very stable line voltage forsensing and reading of the row lines for proper operation of the MRAMsystem. The three dimensional capacitor structures of the presentinvention pack the largest surface area between capacitor plates in thesmallest footprint or die area (IC real estate) to provide additionaldie area for memory elements.

[0038] While the memory device 500 has been described with respect tothe amplifier circuit 400 being connected to the column lines, thememory array 504 is substantially symmetrical and the row and columnlines could be interchanged such that the amplifier circuit 400 couldjust as well be connected to the row lines and the column lines could beread or sensed by the sensor device 508.

[0039] With reference to FIG. 7, in one embodiment, a semiconductor die710 is produced from a silicon wafer 700. The die 710 is an individualpattern, typically rectangular, on a substrate that contains circuitryto perform a specific function. A semiconductor wafer 700 will typicallycontain a repeated pattern of such dies 710 containing the samefunctionality. Die 710 may contain circuitry for the capacitor 100,operational amplifier circuit 400 and memory device 500 or other devicewith which the capacitor 100 may be utilized, as discussed above. Die710 may further contain additional circuitry to extend to such complexdevices as a monolithic processor with multiple functionality. Die 710is typically packaged in a protective casing (not shown) with leadsextending therefrom (not shown) providing access to the circuitry of thedie 710 for unilateral or bilateral communication and control.

[0040] As shown in FIG. 8, two or more dies 710 may be combined, with orwithout protective casing, into a circuit module 800 to enhance orextend the functionality of an individual die 710. Circuit module 800may be a combination of dies 710 representing a variety of functions, ora combination of dies 710 containing the same functionality. Someexamples of a circuit module include memory modules, device drivers,power modules, communication modems, processor modules andapplication-specific modules, multiple voltage supply switches 100 andcontrol circuits 200 and may include multi-layer, multi-chip modules.Circuit module 800 may be a sub-component of a variety of electronicsystems, such as a clock, a television, a cell phone, a personalcomputer, an automobile, an industrial control system, an aircraft andothers. Circuit module 800 will have a variety of leads 810 extendingtherefrom providing unilateral or bilateral communication and control.

[0041]FIG. 9 shows one embodiment of a circuit module as a memory module900. Memory module 900 generally depicts a Single In-line Memory Module(SIMM) or Dual In-line Memory Module (DIAM). A SIMM or DIAM is generallya printed circuit board (PCB) or other support containing a series ofmemory devices. While a SIMM will have a single in-line set of contactsor leads, a DIAM will have a set of leads on each side of the supportwith each set representing separate I/O signals. Memory module 900contains multiple memory devices 910 contained on support 915, thenumber depending upon the desired bus width and the desire for parity.Memory module 900 may contain memory devices 910 on both sides ofsupport 915. Memory module 900 accepts a command signal from an externalcontroller (not shown) on a command link 920 and provides for data inputand data output on data links 930. The command link 920 and data links930 are connected to leads 940 extending from the support 915. Leads 940are shown for conceptual purposes and are not limited to the positionsshown in FIG. 9. The memory module 900 or memory devices 910 may alsoinclude the multiple voltage switch 100 and control circuit 200 toprovide application of different voltages to the memory devices 910 toenable the memory devices to perform different functions or operationsor to place the memory devices 910 in different modes as previouslydescribed.

[0042]FIG. 10 shows an electronic system 1000 containing one or morecircuit modules 800. Electronic system 1000 generally contains a userinterface 1010. User interface 1010 provides a user of the electronicsystem 1000 with some form of control or observation of the results ofthe electronic system 1000. Some examples of user interface 1010 includethe keyboard, pointing device, monitor and printer of a personalcomputer; the tuning dial, display and speakers of a radio; the ignitionswitch and gas pedal of an automobile; and the card reader, keypad,display and currency dispenser of an automated teller machine. Userinterface 1010 may further describe access ports provided to electronicsystem 1000. Access ports are used to connect an electronic system tothe more tangible user interface components previously exemplified. Oneor more of the circuit modules 800 may be a processor providing someform of manipulation, control or direction of inputs from or outputs touser interface 1010, or of other information either preprogrammed into,or otherwise provided to, electronic system 1000. One or more of thecircuit modules 800 may also include a multiple voltage switch 100 andcontrol circuit 200 to facilitate the application of different voltagelevels to other components in the circuit module 800 or to other circuitmodules 800 in the electronic system 1000. As will be apparent from thelists of examples previously given, electronic system 1000 will oftencontain certain mechanical components (not shown) in addition to circuitmodules 800 and user interface 1010. It will be appreciated that the oneor more circuit modules 800 in electronic system 1000 can be replaced bya single integrated circuit. Furthermore, electronic system 1000 may bea sub-component of a larger electronic system.

[0043]FIG. 11 shows one embodiment of an electronic system as a memorysystem 1100. Memory system 1100 contains one or more memory modules 900and a memory controller 1110. Memory controller 1110 provides andcontrols a bidirectional interface between memory system 1100 and anexternal system bus 1120. Memory system 1100 accepts a command signalfrom the external bus 1120 and relays it to the one or more memorymodules 900 on a command link 1130. Memory system 1100 provides for datainput and data output between the one or more memory modules 900 andexternal system bus 1120 on data links 1140. Memory system 1100 mayinclude memory devices such as the MRAM device 500 of FIG. 6.

[0044]FIG. 12 shows a further embodiment of an electronic system as acomputer system 1200. Computer system 1200 contains a processor 1210 anda memory system 1100 housed in a computer unit 1205. Computer system1200 is but one example of an electronic system containing anotherelectronic system, i.e. memory system 1100, as a sub-component. Computersystem 1200 optionally contains user interface components. Depicted inFIG. 12 are a keyboard 1220, a pointing device 1230, a monitor 1240, aprinter 1250 and a bulk storage device 1260. It will be appreciated thatother components are often associated with computer system 1200 such asmodems, device driver cards, additional storage devices, etc. It willfurther be appreciated that the processor 1210 and memory system 1100 ofcomputer system 1200 can be incorporated on a single integrated circuit.Such single package processing units reduce the communication timebetween the processor 1210 and the memory system 1100.

[0045] While the three dimensional capacitor structures of the presentinvention have been described with respect to use in an amplifiercircuit and memory circuits, it should be noted that the threedimensional capacitor structures may be used in any circuit where arelatively large capacitance value is needed but design constraints oravailable die area necessitate that the capacitor occupies the smallestpossible footprint on the die or wafer. The present invention packs thelargest surface area between capacitor plates into the smallestfootprint on a semiconductor die or wafer.

[0046] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. Therefore, it is intended that this invention be limited onlyby the claims and the equivalents thereof.

What is claimed is:
 1. A capacitor, comprising: a substrate; a layer ofconductive material formed on the substrate, the layer of conductivematerial including at least a first portion and a second portion,wherein the first portion and the second portion are arranged in apredetermined pattern relative to one another to provide a maximumamount of juxtaposed surface area between the first and second portions;and a layer of insulation material disposed at least between the firstand second portions.
 2. The capacitor of claim 1, wherein thepredetermined pattern is a substantially comb-like structure wherein theteeth of the combs of the first portion and the second portion areinterleaved.
 3. The capacitor of claim 2, wherein the teeth of each ofthe combs of the first and second portions have a selected height andlength to provide a selected capacitance.
 4. The capacitor of claim 1,wherein the predetermined pattern forms a substantially serpentine gapof a selected width between the first and second portions to provide aselected capacitance between the first and second portions.
 5. Acapacitor, comprising: a substrate; a layer of conductive materialformed on the substrate, the layer of conductive material including atleast a first portion and a second portion, wherein the first portionand the second portion are arranged in a predetermined pattern relativeto one another to provide a maximum amount of juxtaposed surface area; alayer of insulation material disposed between and over the first andsecond portions; a reference plate disposed on the layer of insulationmaterial and over the first and second portions; and at least onecontact electrically connecting the reference plate to one of the firstor second portions.
 6. The capacitor of claim 5, wherein the at leastone contact is a plug of conductive material disposed in a openingthrough the layer of insulation.
 7. The capacitor of claim 6, whereinthe plug is formed from one of tungsten, copper, aluminum or an alloy oftungsten, copper and aluminum.
 8. A capacitor, comprising: a substrate;a layer of conductive material formed on the substrate, the layer ofconductive material including at least a first portion and a secondportion, wherein the first portion and the second portion each have asubstantially comb-like structure with a plurality of teeth, the teethof the first portion and the second portion being interleaved and eachtooth including a pair of sidewalls, each sidewall except an outsidesidewall of an end tooth facing a sidewall of a tooth of the otherportion to provide a maximum amount of juxtaposed surface area; a layerof insulation material disposed between and over the first and secondportions; a reference plate disposed on the layer of insulation materialand over the first and second portions; and at least one contactelectrically connecting the reference plate to one of the first orsecond portions.
 9. The capacitor of claim 8, wherein the sidewall ofeach tooth has a selected height and length to provide a selectedcapacitance.
 10. The capacitor of claim 8, further comprising asubstantially serpentine gap of a selected width between the first andsecond portions to provide a selected capacitance between the first andsecond portions.
 11. A capacitor, comprising: a substrate; a firstreference plate of conductive material disposed on the substrate; afirst layer of insulation material covering the first reference plate; alayer of conductive material formed on the first layer of insulationmaterial, the layer of conductive material including at least a firstportion and a second portion, wherein the first portion and the secondportion are arranged in a predetermined pattern relative to one anotherto provide a maximum amount of juxtaposed surface area; a second layerof insulation material disposed between and over the first and secondportions; a second reference plate disposed on the second layer ofinsulation material and over the first and second portions; and at leastone contact electrically connecting at least one of the first and secondreference plates to at least one of the first or second portions. 12.The capacitor of claim 11, wherein the at least one contact is a plug ofconductive material disposed in a opening through at least one of thefirst or second layers of insulation.
 13. The capacitor of claim 12,wherein the plug is formed from one of tungsten, copper, aluminum or analloy of tungsten, copper and aluminum.
 14. A capacitor, comprising: asubstrate; a first reference plate of conductive material disposed onthe substrate; a first layer of insulation material covering the firstreference plate; a layer of conductive material formed on the substrate,the layer of conductive material including at least a first portion anda second portion, wherein the first portion and the second portion eachhave a substantially comb-like structure with a plurality of teeth, theteeth of the first portion and the second portion being interleaved andeach tooth including a pair of sidewalls, each sidewall except anoutside sidewall of an end tooth facing a sidewall of a tooth of theother portion to provide a maximum amount of juxtaposed surface area; asecond layer of insulation material disposed between and over the firstand second portions; a second reference plate disposed on the secondlayer of insulation material and over the first and second portions; andat least one contact electrically connecting at least one of the firstand second reference plates to at least one of the first or secondportions.
 15. The capacitor of claim 14, wherein the sidewalls of eachtooth has a selected height and length to provide a selectedcapacitance.
 16. The capacitor of claim 14, wherein the interleavedcomb-like structures form a substantially serpentine gap of a selectedwidth between the first and second portions to provide a selectedcapacitance between the first and second portions.
 17. A capacitor,comprising: a substrate; a first plurality of interconnected strips of aconductive material formed on the substrate; a second plurality ofinterconnected strips of conductive material formed on the substrate,wherein the second plurality of strips are interleaved with the firstplurality of strips; and insulation material disposed between each ofthe first plurality of strips and each of the interleaved secondplurality of strips.
 18. The capacitor of claim 17, wherein each striphas a sidewall and wherein the first plurality of strips and the secondplurality of strips are interleaved in a predetermined pattern toprovide a maximum of juxtaposed sidewall surface area of the firstplurality of strips and the second plurality of strips.
 19. Thecapacitor of claim 17, wherein each strip has a sidewall of a selectedheight and length and wherein the first plurality of strips and thesecond plurality of strips are interleaved in a predetermined pattern toprovide the maximum capacitance per selected area of the substrate. 20.A capacitor, comprising: a first substantial comb-like structure ofconductive material including a plurality of teeth; and a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein the teeth of the second substantiallycomb-like structure are interleaved with the teeth of the firstsubstantially comb-like structure, and wherein each tooth of the firstand second comb-like structures have a pair of sidewalls, each sidewallhaving a selected surface area and each of the teeth of the firstcomb-like structure and the second comb-like structure being separatedby a gap of a chosen width to provide a predetermined capacitance. 21.The capacitor of claim 20, wherein the first comb-like structure and thesecond comb-like structure are interleaved to provide a maximum amountof juxtaposed sidewall surface area between the teeth of the first andsecond comb-like structures.
 22. A capacitor, comprising: a firstsubstantial comb-like structure of conductive material including aplurality of teeth; a second substantially comb-like structure ofconductive material including a plurality of teeth, wherein the teeth ofthe second substantially comb-like structure interleave the teeth of thefirst substantially comb-like structure, and wherein each tooth of thefirst and second comb-like structures have a pair of sidewalls, eachsidewall having a selected surface area and each of the teeth of thefirst comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance; a reference plate of a conductive material disposedadjacent the first and second comb-like structures at a selecteddistance therefrom; a layer of insulation material disposed between thereference plate and the first and second comb-like structures; and atleast one contact electrically connecting the reference plate and one ofthe first and second comb-like structures.
 23. The capacitor of claim22, wherein the at least one contact is formed through an opening formedin the layer of insulation and comprises at least one of tungsten,copper and aluminum.
 24. A capacitor, comprising: a first substantialcomb-like structure of conductive material including a plurality ofteeth; and a second substantially comb-like structure of conductivematerial including a plurality of teeth, wherein each tooth of the firstand second comb-like structures have a pair of sidewalls with a selectedsurface area and wherein the first comb-like structure and the secondcomb-like structure are interleaved to provide a maximum amount ofjuxtaposed sidewall surface area between the teeth of the first andsecond comb-like structures.
 25. The capacitor of claim 24, wherein thefirst comb-like structure and the second comb-like structure areseparated by a gap and wherein the width of the gap and the surface areaof each of the sidewalls are selected to provide a predeterminedcapacitance.
 26. A capacitor, comprising: a first substantial comb-likestructure of conductive material including a plurality of teeth; asecond substantially comb-like structure of conductive materialincluding a plurality of teeth, wherein the teeth of the secondsubstantially comb-like structure are interleaved with the teeth of thefirst substantially comb-like structure, and wherein each tooth of thefirst and second comb-like structures have a pair sidewalls, eachsidewall having a selected surface area and each of the teeth of thefirst comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance; a first reference plate of a conductive material disposedon one side of the first and second comb-like structures facing theplurality of teeth at a selected distance therefrom; a first layer ofinsulation material disposed between the first reference plate and thefirst and second comb-like structures; a second reference plate ofconductive material disposed on another side of the first and secondcomb-like structures facing the plurality of teeth at the selecteddistance; a second layer of insulation material disposed between thesecond reference plate and the first and second comb-like structures;and at least one contact electrically connecting at least one of thefirst and second reference plates to at least one of the first or secondcomb-like structures.
 27. A capacitor, comprising: a layer of conductivematerial including at least a first portion and a second portion,wherein the first portion and the second portion are arranged in apredetermined pattern relative to one another to provide a maximumamount of capacitance per area; and a layer of insulation materialdisposed at least between the first and second portions.
 28. Thecapacitor of claim 27, wherein the layer of conductive materialcomprises tungsten.
 29. The capacitor of claim 27, wherein the layer ofconductive material comprises: a first layer of metalization orpolysilicon; a layer of tungsten disposed on the layer of metalizationor polysilicon; and a second layer of metalization or polysilicon.
 30. Acapacitor, comprising: a layer of conductive material, the layer ofconductive material including at least a first portion and a secondportion, wherein the first portion and the second portion are arrangedin a predetermined pattern relative to one another to provide a selectedamount of juxtaposed surface area between the first and second portionsand the first and second portions being separated by a gap of a chosenwidth to provide a predetermined capacitance; and a layer of insulationmaterial disposed at least between the first and second portions.
 31. Acapacitor, comprising: a first substantially comb-like structure ofconductive material including a plurality of teeth; and a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein each tooth of the first and second comb-likestructures have a pair of sidewalls with a selected surface area andwherein the first comb-like structure and the second comb-like structureare interleaved to provide a maximum capacitance.
 32. The capacitor ofclaim 31, wherein the first and second substantially comb-likestructures each comprise tungsten.
 33. The capacitor of claim 31,wherein the first and second substantially comb-like structures eachcomprise: a first layer of metalization or polysilicon; a layer oftungsten disposed on the layer of metalization or polysilicon; and asecond layer of metalization or polysilicon.
 34. An integrated circuit,comprising: a substrate an amplifier formed on the substrate; and acapacitor formed on the substrate and connected to an input of theamplifier, the capacitor comprising: a first substantially comb-likestructure of conductive material including a plurality of teeth; and asecond substantially comb-like structure of conductive materialincluding a plurality of teeth, wherein the teeth of the secondsubstantially comb-like structure are interleaved with the teeth of thefirst substantially comb-like structure, and wherein each tooth of thefirst and second comb-like structures have a pair of sidewalls, eachsidewall having a selected surface area and each of the teeth of thefirst comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance.
 35. An integrated circuit, comprising: an amplifier; and acapacitor connected to an input of the amplifier, the capacitorcomprising: a first substantially comb-like structure of conductivematerial including a plurality of teeth; a second substantiallycomb-like structure of conductive material including a plurality ofteeth, wherein the teeth of the second substantially comb-like structureare interleaved with the teeth of the first substantially comb-likestructure, and wherein each tooth of the first and second comb-likestructures have a pair of sidewalls, each sidewall having a selectedsurface area and each of the teeth of the first comb-like structure andthe second comb-like structure being separated by a gap of a chosenwidth to provide a predetermined capacitance; a reference plate of aconductive material disposed adjacent the first and second comb-likestructures at a selected distance therefrom; a layer of insulationmaterial disposed between the reference plate and the first and secondcomb-like structures; and at least one contact electrically connectingthe reference plate and one of the first and second comb-likestructures.
 36. The integrated circuit of claim 31, wherein the at leastone contact is formed through an opening formed in the layer ofinsulation and comprises at least one of tungsten, copper and aluminum.37. An integrated circuit, comprising: an electronic circuit; and acapacitor connected to the electronic circuit, the capacitor comprising:a first substantially comb-like structure of conductive materialincluding a plurality of teeth; a second substantially comb-likestructure of conductive material including a plurality of teeth, whereinthe teeth of the second substantially comb-like structure areinterleaved with the teeth of the first substantially comb-likestructure, and wherein each tooth of the first and second comb-likestructures have a pair of sidewalls, each sidewall having a selectedsurface area and each of the teeth of the first comb-like structure andthe second comb-like structure being separated by a gap of a chosenwidth to provide a predetermined capacitance; a first reference plate ofa conductive material disposed on one side of the first and secondcomb-like structures facing the plurality of teeth at a selecteddistance therefrom; a first layer of insulation material disposedbetween the first reference plate and the first and second comb-likestructures; a second reference plate of conductive material disposed onanother side of the first and second comb-like structures facing theplurality of teeth at the selected distance; a second layer ofinsulation material disposed between the second reference plate and thefirst and second comb-like structures; and at least one contactelectrically connecting at least one of the first and second referenceplates to at least one of the first or second comb-like structures. 38.An integrated circuit, comprising: a substrate an amplifier formed onthe substrate; and a capacitor formed on the substrate and connected toan input of the integrated circuit, the capacitor comprising: a layer ofconductive material, the layer of conductive material including at leasta first portion and a second portion, wherein the first portion and thesecond portion are arranged in a predetermined pattern relative to oneanother to provide a maximum amount of juxtaposed surface area betweenthe first and second portions; and a layer of insulation materialdisposed at least between the first and second portions.
 39. Theintegrated circuit of claim 34, wherein the predetermined pattern is asubstantially comb-like structure wherein the teeth of the combs of thefirst portion and the second portion are interleaved.
 40. An integratedcircuit, comprising: an amplifier; a capacitor connected to an input ofthe amplifier, the capacitor comprising: a substrate; a layer ofconductive material formed on the substrate, the layer of conductivematerial including at least a first portion and a second portion,wherein the first portion and the second portion each have asubstantially comb-like structure with a plurality of teeth, the teethof the first portion and the second portion being interleaved and eachtooth including a pair of sidewalls, each sidewall, except an outsidesidewall of an end tooth, facing a sidewall of a tooth of the otherportion to provide a maximum amount of juxtaposed surface area; a layerof insulation material disposed between and over the first and secondportions; a reference plate disposed on the layer of insulation materialand over the first and second portions; and at least one contactelectrically connecting the reference plate to one of the first orsecond portions.
 41. An integrated circuit, comprising: a substrate; anelectronic circuit formed on the substrate; a capacitor connected to theelectronic circuit, the capacitor comprising: a first substantiallycomb-like structure of conductive material including a plurality ofteeth; and a second substantially comb-like structure of conductivematerial including a plurality of teeth, wherein each tooth of the firstand second comb-like structures have a pair of sidewalls with a selectedsurface area and wherein the first comb-like structure and the secondcomb-like structure are interleaved to provide a maximum amount ofjuxtaposed sidewall surface area between the teeth of the first andsecond comb-like structures.
 42. An integrated circuit, comprising: asubstrate an electronic circuit formed on the substrate; a capacitorformed on the substrate and connected to the electronic circuit, thecapacitor comprising: a layer of conductive material formed, the layerof conductive material including at least a first portion and a secondportion, wherein the first portion and the second portion are arrangedin a predetermined pattern relative to one another to provide a maximumamount of capacitance; and a layer of insulation material disposed atleast between the first and second portions.
 43. A memory system,comprising: an array of memory elements, each memory element beingconnected by one of a plurality of row lines and by one of a pluralityof column lines; an amplifier connected to at least one of each of theplurality of column lines or to at least one of each of the plurality ofrow lines; a capacitor connected to an input of each amplifier, eachcapacitor comprising: a first substantially comb-like structure ofconductive material including a plurality of teeth; and a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein the teeth of the second substantiallycomb-like structure are interleaved with the teeth of the firstsubstantially comb-like structure, and wherein each tooth of the firstand second comb-like structures have a pair of sidewalls, each sidewallhaving a selected surface area and each of the teeth of the firstcomb-like structure and the second comb-like structure being separatedby a gap of a chosen width to provide a predetermined capacitance.
 44. Amemory system, comprising: an array of memory elements, each memoryelement being connected by one of a plurality of row lines and by one ofa plurality of column lines; at least one multiplexer connected to oneof the plurality of column lines or the plurality of row lines; at leastone amplifier connected to the at least one multiplexer; a capacitorconnected to an input of the at least one amplifier, the capacitorcomprising: a first substantially comb-like structure of conductivematerial including a plurality of teeth; and a second substantiallycomb-like structure of conductive material including a plurality ofteeth, wherein the teeth of the second substantially comb-like structureare interleaved with the teeth of the first substantially comb-likestructure, and wherein each tooth of the first and second comb-likestructures have a pair of sidewalls, each sidewall having a selectedsurface area and each of the teeth of the first comb-like structure andthe second comb-like structure being separated by a gap of a chosenwidth to provide a predetermined capacitance.
 45. A memory system,comprising: an array of memory elements, each memory element beingconnected by one of a plurality of row lines and by one of a pluralityof column lines; an amplifier connected to at least one of each of theplurality of column lines or to at least one of each of the plurality ofrow lines; a capacitor connected to an input of each amplifier, eachcapacitor comprising: a first substantially comb-like structure ofconductive material including a plurality of teeth; a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein the teeth of the second substantiallycomb-like structure are interleaved with the teeth of the firstsubstantially comb-like structure, and wherein each tooth of the firstand second comb-like structures have a pair of sidewalls, each sidewallhaving a selected surface area and each of the teeth of the firstcomb-like structure and the second comb-like structure being separatedby a gap of a chosen width to provide a predetermined capacitance; areference plate of a conductive material disposed adjacent the first andsecond comb-like structures at a selected distance therefrom; a layer ofinsulation material disposed between the reference plate and the firstand second comb-like structures; and at least one contact electricallyconnecting the reference plate and one of the first and second comb-likestructures.
 46. A memory system, comprising: an array of memoryelements, each memory element being connected by one of a plurality ofrow lines and by one of a plurality of column lines; an amplifierconnected to at least one of each of the plurality of column lines or toat least one of each of the plurality of row lines; a capacitorconnected to an input of each amplifier, each capacitor comprising: afirst substantially comb-like structure of conductive material includinga plurality of teeth; a second substantially comb-like structure ofconductive material including a plurality of teeth, wherein the teeth ofthe second substantially comb-like structure are interleaved with theteeth of the first substantially comb-like structure, and wherein eachtooth of the first and second comb-like structures have a pairsidewalls, each sidewall having a selected surface area and each of theteeth of the first comb-like structure and the second comb-likestructure being separated by a gap of a chosen width to provide apredetermined capacitance; a first reference plate of a conductivematerial disposed on one side of the first and second comb-likestructures facing the plurality of teeth at a selected distancetherefrom; a first layer of insulation material disposed between thefirst reference plate and the first and second comb-like structures; asecond reference plate of conductive material disposed on another sideof the first and second comb-like structures facing the plurality ofteeth at the selected distance; a second layer of insulation materialdisposed between the second reference plate and the first and secondcomb-like structures; and at least one contact electrically connectingat least one of the first and second reference plates to at least one ofthe first or second comb-like structures.
 47. A memory system,comprising: an array of memory elements, each memory element beingconnected by one of a plurality of row lines and by one of a pluralityof column lines; an amplifier connected to at least one of each of theplurality of column lines or to at least one of each of the plurality ofrow lines; a capacitor connected to an input of each amplifier, eachcapacitor comprising: a layer of conductive material formed on thesubstrate, the layer of conductive material including at least a firstportion and a second portion, wherein the first portion and the secondportion are arranged in a predetermined pattern relative to one anotherto provide a maximum amount of juxtaposed surface area between the firstand second portions; and a layer of insulation material disposed atleast between the first and second portions.
 48. The memory system ofclaim 47, wherein the layer of conductive material comprises tungsten.49. A memory system, comprising: an array of memory elements, eachmemory element being connected by one of a plurality of row lines andone of a plurality of column lines; an amplifier connected to at leastone of each of the plurality of row lines or to at least one of each ofthe plurality of column lines; a capacitor connected to an input of eachamplifier, each capacitor comprising: a first substantially comb-likestructure of conductive material including a plurality of teeth; and asecond substantially comb-like structure of conductive materialincluding a plurality of teeth, wherein each tooth of the first andsecond comb-like structures have a pair of sidewalls with a selectedsurface area and wherein the first comb-like structure and the secondcomb-like structure are interleaved to provide a maximum amount ofjuxtaposed sidewall surface area between the teeth of the first andsecond comb-like structures.
 50. A memory system, comprising: an arrayof memory elements, each memory element being connected by one of aplurality of row lines and by one of a plurality of column lines; anamplifier connected to at least one of each of the plurality of columnlines or to at least one of each of the plurality of row lines; acapacitor connected to an input of each amplifier, each capacitorcomprising: a layer of conductive material formed on the substrate, thelayer of conductive material including at least a first portion and asecond portion, wherein the first portion and the second portion arearranged in a predetermined pattern relative to one another to provide amaximum amount of capacitance per a given area; and a layer ofinsulation material disposed at least between the first and secondportions.
 51. The memory system of claim 50, wherein the layer ofconductive material comprises: a first layer of metalization orpolysilicon; a layer of tungsten disposed on the first layer ofmetalization or polysilicon; and a second layer of metalization orpolysilicon disposed on the layer of tungsten.
 52. The memory system ofclaim 50, wherein the layer of conductive material comprises tungsten.53. A semiconductor die, comprising: a substrate; and an integratedcircuit formed on the substrate, wherein the integrated circuitcomprises at least one capacitor, the at least one capacitor comprising:a layer of conductive material formed on the substrate, the layer ofconductive material including at least a first portion and a secondportion, wherein the first portion and the second portion are arrangedin a predetermined pattern relative to one another to provide a maximumamount of juxtaposed surface area between the first and second portions;and a layer of insulation material disposed at least between the firstand second portions.
 54. A semiconductor die, comprising: a substrate;and an integrated circuit formed on the substrate, wherein theintegrated circuit comprises at least one capacitor and wherein the atleast one capacitor comprises: a first substantially comb-like structureof conductive material including a plurality of teeth; and a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein the teeth of the second substantiallycomb-like structure are interleaved with the teeth of the firstsubstantially comb-like structure, and wherein each tooth of the firstand second comb-like structures have a pair of sidewalls, each sidewallhaving a selected surface area and each of the teeth of the firstcomb-like structure and the second comb-like structure being separatedby a gap of a chosen width to provide a predetermined capacitance.
 55. Asemiconductor die, comprising: a substrate; and an integrated circuitformed on the substrate, wherein the integrated circuit comprises atleast one capacitor and wherein the at least one capacitor comprises: afirst substantially comb-like structure of conductive material includinga plurality of teeth; a second substantially comb-like structure ofconductive material including a plurality of teeth, wherein the teeth ofthe second substantially comb-like structure interleave the teeth of thefirst substantially comb-like structure, and wherein each tooth of thefirst and second comb-like structures have a pair of sidewalls, eachsidewall having a selected surface area and each of the teeth of thefirst comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance; a reference plate of a conductive material disposedadjacent the first and second comb-like structures at a selecteddistance therefrom; a layer of insulation material disposed between thereference plate and the first and second comb-like structures; and atleast one contact electrically connecting the reference plate and one ofthe first and second comb-like structures.
 56. A semiconductor die,comprising: a substrate; and an integrated circuit formed on thesubstrate, wherein the integrated circuit comprises at least onecapacitor and wherein the at least one capacitor comprises: a firstreference plate of a conductive material disposed on the substrate; afirst layer of insulation material disposed over the first referenceplate; a first substantially comb-like structure of conductive materialformed on the first layer of insulation material including a pluralityof teeth; a second substantially comb-like structure of conductivematerial formed on the first layer of insulation including a pluralityof teeth, wherein the teeth of the second substantially comb-likestructure are interleaved with the teeth of the first substantiallycomb-like structure, and wherein each tooth of the first and secondcomb-like structures have a pair sidewalls, each sidewall having aselected surface area and each of the teeth of the first comb-likestructure and the second comb-like structure being separated by a gap ofa chosen width to provide a predetermined capacitance; a second layer ofinsulation material disposed over the first and second comb-likestructures; a second reference plate of conductive material disposedover the second layer of insulation material; and at least one contactelectrically connecting at least one of the first and second referenceplates to at least one of the first or second comb-like structures. 57.A semiconductor die, comprising: a substrate; and an integrated circuitformed on the substrate, wherein the integrated circuit comprises atleast one capacitor and wherein the at least one capacitor comprises: afirst substantially comb-like structure of conductive material formed onthe substrate including a plurality of teeth; and a second substantiallycomb-like structure of conductive material formed on the substrateincluding a plurality of teeth, wherein each tooth of the first andsecond comb-like structures have a pair of sidewalls with a selectedsurface area and wherein the first comb-like structure and the secondcomb-like structure are interleaved to provide a maximum amount ofjuxtaposed sidewall surface area between the teeth of the first andsecond comb-like structures.
 58. A semiconductor die, comprising: asubstrate; and an integrated circuit formed on the substrate, whereinthe integrated circuit comprises at least one capacitor and wherein theat least one capacitor comprises: a layer of conductive material formedon the substrate, the layer of conductive material including at least afirst portion and a second portion, wherein the first portion and thesecond portion are arranged in a predetermined pattern relative to oneanother to provide a maximum amount of capacitance; and a layer ofinsulation material disposed at least between the first and secondportions.
 59. An electronic system, comprising: a processor; a memorydevice coupled to the processor, the memory device comprising an arrayof memory elements, each memory element being connected by one of aplurality of row lines and by one of a plurality of column lines; anamplifier connected to at least one of each of the plurality of rowlines or to at least one of the plurality of column lines; a capacitorconnected to an input of each amplifier, each capacitor comprising: afirst substantially comb-like structure of conductive material includinga plurality of teeth; and a second substantially comb-like structure ofconductive material including a plurality of teeth, wherein the teeth ofthe second substantially comb-like structure are interleaved with theteeth of the first substantially comb-like structure, and wherein eachtooth of the first and second comb-like structures have a pair ofsidewalls, each sidewall having a selected surface area and each of theteeth of the first comb-like structure and the second comb-likestructure being separated by a gap of a chosen width to provide apredetermined capacitance.
 60. An electronic system, comprising: aprocessor; a memory device coupled to the processor, the memory devicecomprising an array of memory elements, each memory element beingconnected by one of a plurality of row lines and by one of a pluralityof column lines; an amplifier connected to at least one of each of theplurality of row lines or to at least one of the plurality of columnlines; a capacitor connected to an input of each amplifier, eachcapacitor comprising: a layer of conductive material formed on thesubstrate, the layer of conductive material including at least a firstportion and a second portion, wherein the first portion and the secondportion are arranged in a predetermined pattern relative to one anotherto provide a maximum amount of juxtaposed surface area between the firstand second portions; and a layer of insulation material disposed atleast between the first and second portions.
 61. An electronic system,comprising: a processor; a memory device coupled to the processor, thememory device comprising an array of memory elements, each memoryelement being connected by one of a plurality of row lines and by one ofa plurality of column lines; at least one multiplexer connected to oneof the plurality of column lines or the plurality of row lines; at leastone amplifier connected to the at least one multiplexer; a capacitorconnected to an input of each amplifier, each capacitor comprising: alayer of conductive material formed on the substrate, the layer ofconductive material including at least a first portion and a secondportion, wherein the first portion and the second portion are arrangedin a predetermined pattern relative to one another to provide a maximumamount of capacitance per a given area; and a layer of insulationmaterial disposed at least between the first and second portions.
 62. Anelectronic system, comprising: a processor; a memory device coupled tothe processor, the memory device comprising an array of memory elements,each memory element being connected by one of a plurality of row linesand by one of a plurality of column lines; an amplifier connected to atleast one of each of the plurality of row lines or to at least one ofthe plurality of column lines; a capacitor connected to an input of eachamplifier, each capacitor comprising: a layer of conductive materialformed on the substrate, the layer of conductive material including atleast a first portion and a second portion, wherein the first portionand the second portion are arranged in a predetermined pattern relativeto one another to provide a maximum amount of capacitance per a givenarea; and a layer of insulation material disposed at least between thefirst and second portions.
 63. An electronic system, comprising: aprocessor; a memory device coupled to the processor, the memory devicecomprising an array of memory elements, each memory element beingconnected by one of a plurality of row lines and by one of a pluralityof column lines; an amplifier connected to at least one of each of theplurality of row lines or to at least one of the plurality of columnlines; a capacitor connected to an input of each amplifier, eachcapacitor comprising: a first substantially comb-like structure ofconductive material including a plurality of teeth; a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein the teeth of the second substantiallycomb-like structure are interleaved with the teeth of the firstsubstantially comb-like structure, and wherein each tooth of the firstand second comb-like structures have a pair of sidewalls, each sidewallhaving a selected surface area and each of the teeth of the firstcomb-like structure and the second comb-like structure being separatedby a gap of a chosen width to provide a predetermined capacitance; areference plate of a conductive material disposed adjacent the first andsecond comb-like structures at a selected distance therefrom; a layer ofinsulation material disposed between the reference plate and the firstand second comb-like structures; and at least one contact electricallyconnecting the reference plate and one of the first and second comb-likestructures.
 64. A method of making a capacitor, comprising: depositingat least one layer of conductive material on a substrate; and removingmaterial from the at least one layer of conductive material to form afirst portion and a second portion arranged in a predetermined patternrelative to one another to provide a maximum amount of juxtaposedsurface area between the first and second portions.
 65. The method ofclaim 64, wherein depositing at least one layer of conductive materialcomprises depositing a layer of tungsten.
 66. The method of claim 64,wherein depositing at least one layer of conductive material comprises:depositing a first layer of metalization or polysilicon; depositing alayer of tungsten on the first layer of metalization; and depositing asecond layer of metalization or polysilicon.
 67. A method of making acapacitor, comprising: depositing at least one layer of conductivematerial; removing a portion of the at least one layer of conductivematerial to form a first substantially comb-like structure including aplurality of teeth; and removing another portion of the at least onelayer of conductive material to form a second substantially comb-likestructure including a plurality of teeth, wherein the teeth of thesecond substantially comb-like structure are interleaved with the teethof the first substantially comb-like structure, and wherein each toothof the first and second comb-like structures have a pair of sidewalls,each sidewall having a selected surface area and each of the teeth ofthe first comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance.
 68. A method of making a capacitor, comprising depositingat least one layer of conductive material; removing a portion of the atleast one layer of conductive material to form a first substantiallycomb-like structure including a plurality of teeth; and removing anotherportion of the at least one layer of conductive material to form asecond substantially comb-like structure including a plurality of teeth,wherein each tooth of the first and second comb-like structures have apair of sidewalls with a selected surface area and wherein the firstcomb-like structure and the second comb-like structure are interleavedto provide a maximum amount of juxtaposed sidewall surface area betweenthe teeth of the first and second comb-like structures.
 69. A method ofmaking a capacitor, comprising: depositing at least one layer ofconductive material on a substrate; removing material from the layer ofconductive material to form a first portion and second portion arrangedin a predetermined pattern relative to one another to provide a maximumamount of capacitance per area of the substrate; and depositing a layerof insulation material at least between the first and second portions.70. A method of making a memory device, comprising: forming an array ofmemory elements with each memory element being connected by one of aplurality of row lines and by one of a plurality of column lines;forming an amplifier connected to at least one of each of the pluralityof column lines or to at least one each of the plurality of row lines;forming a capacitor connected to an input of each amplifier, forming thecapacitor comprising: depositing at least one layer of conductivematerial on a substrate; and removing material from the at least onelayer of conductive material to form a first portion and second portionarranged in a predetermined pattern relative to one another to provide amaximum amount of juxtaposed surface area between the first and secondportions.
 71. A method of making a memory device, comprising: forming anarray of memory elements with each memory element being connected by oneof a plurality of row lines and by one of a plurality of column lines;forming an amplifier connected to at least one of each of the pluralityof column lines or to at least one each of the plurality of row lines;forming a capacitor connected to an input of each amplifier, forming thecapacitor comprising: depositing at least one layer of conductivematerial; removing a portion of the at least one layer of conductivematerial to form a first substantially comb-like structure including aplurality of teeth; and removing another portion of the at least onelayer of conductive material to form a second substantially comb-likestructure including a plurality of teeth, wherein the teeth of thesecond substantially comb-like structure are interleaved with the teethof the first substantially comb-like structure, and wherein each toothof the first and second comb-like structures have a pair of sidewalls,each sidewall having a selected surface area and each of the teeth ofthe first comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance.
 72. A method of making a memory device, comprising: formingan array of memory elements with each memory element being connected byone of a plurality of row lines and by one of a plurality of columnlines; forming an amplifier connected to at least one of each of theplurality of column lines or to at least one each of the plurality ofrow lines; forming a capacitor connected to an input of each amplifier,forming the capacitor comprising: depositing at least one layer ofconductive material; removing a portion of the at least one layer ofconductive material to form a first substantially comb-like structureincluding a plurality of teeth; and removing another portion of the atleast one layer of conductive material to form a second substantiallycomb-like structure including a plurality of teeth, wherein each toothof the first and second comb-like structures have a pair of sidewallswith a selected surface area and wherein the first comb-like structureand the second comb-like structure are interleaved to provide a maximumamount of juxtaposed sidewall surface area between the teeth of thefirst and second comb-like structures.
 73. A method of making a memorydevice, comprising: forming an array of memory elements with each memoryelement being connected by one of a plurality of row lines and by one ofa plurality of column lines; forming an amplifier connected to at leastone of each of the plurality of column lines or to at least one each ofthe plurality of row lines; forming a capacitor connected to an input ofeach amplifier, forming the capacitor comprising: depositing at leastone layer of conductive material on a substrate; removing material fromthe layer of conductive material to form a first portion and secondportion arranged in a predetermined pattern relative to one another toprovide a maximum amount of capacitance per area of the substrate; anddepositing a layer of insulation material at least between the first andsecond portions.
 74. A method of making a memory device, comprising:forming an array of memory elements with each memory element beingconnected by one of a plurality of row lines and by one of a pluralityof column lines; forming at least one multiplexer connected to each ofthe plurality of column lines or to each of the plurality of row lines;forming at least one amplifier connected to the at least onemultiplexer; forming a capacitor connected to an input of eachamplifier, forming the capacitor comprising: depositing at least onelayer of conductive material on a substrate; removing material from thelayer of conductive material to form a first portion and second portionarranged in a predetermined pattern relative to one another to provide amaximum amount of capacitance per area per area of the substrate; anddepositing a layer of insulation material at least between the first andsecond portions.
 75. A method of making an electronic system,comprising: forming a processor; forming a memory device coupled to theprocessor, the memory device comprising an array of memory elements,each memory element being connected by one of a plurality of row linesand by one of a plurality of column lines; forming an amplifierconnected to at least one of each of the plurality of row lines or toeach of the plurality of column lines; forming a capacitor connected toan input of each amplifier, forming the capacitor comprising: depositingat least one layer of conductive material on a substrate; and removingmaterial from the layer of conductive material to form a first portionand second portion arranged in a predetermined pattern relative to oneanother to provide a maximum amount of juxtaposed surface area betweenthe first and second portions.
 76. A method of making an electronicsystem, comprising: forming a processor; forming a memory device coupledto the processor, the memory device comprising an array of memoryelements, each memory element being connected by one of a plurality ofrow lines and by one of a plurality of column lines; forming anamplifier connected to at least one of each of the plurality of rowlines or to each of the plurality of column lines; forming a capacitorconnected to an input of each amplifier, forming the capacitorcomprising: depositing at least one layer of conductive material;removing a portion of the at least one layer of conductive material toform a first substantially comb-like structure including a plurality ofteeth; and removing another portion of the at least one layer ofconductive material to form a second substantially comb-like structureincluding a plurality of teeth, wherein the teeth of the secondsubstantially comb-like structure are interleaved with the teeth of thefirst substantially comb-like structure, and wherein each tooth of thefirst and second comb-like structures have a pair of sidewalls, eachsidewall having a selected surface area and each of the teeth of thefirst comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance.
 77. A method of making an electronic system, comprising:forming a processor; forming a memory device coupled to the processor,the memory device comprising an array of memory elements, each memoryelement being connected by one of a plurality of row lines and by one ofa plurality of column lines; forming an amplifier connected to at leastone of each of the plurality of row lines or to each of the plurality ofcolumn lines; forming a capacitor connected to an input of eachamplifier, forming the capacitor comprising: depositing at least onelayer of conductive material; removing a portion of the at least onelayer of conductive material to form a first substantially comb-likestructure including a plurality of teeth; and removing another portionof the at least one layer of conductive material to form a secondsubstantially comb-like structure including a plurality of teeth,wherein each tooth of the first and second comb-like structures have apair of sidewalls with a selected surface area and wherein the firstcomb-like structure and the second comb-like structure are interleavedto provide a maximum amount of juxtaposed sidewall surface area betweenthe teeth of the first and second comb-like structures.
 78. A method ofmaking an electronic system, comprising: forming a processor; forming amemory device coupled to the processor, the memory device comprising anarray of memory elements, each memory element being connected by one ofa plurality of row lines and by one of a plurality of column lines;forming an amplifier connected to at least one of each of the pluralityof row lines or to each of the plurality of column lines; forming acapacitor connected to an input of each amplifier, forming the capacitorcomprising: depositing at least one layer of conductive material on asubstrate; removing material from the layer of conductive material toform a first portion and second portion arranged in a predeterminedpattern relative to one another to provide a maximum amount ofcapacitance per area of the substrate; and depositing a layer ofinsulation material at least between the first and second portions. 79.A method for correcting offset voltage in an amplifier, comprising:connecting an output of the amplifier to an inverting input of theamplifier; connecting an offset capacitor between the inverting input ofthe amplifier and a non-inverting input of the amplifier, wherein thecapacitor comprises a layer of conductive material including at least afirst portion and a second portion, wherein the first portion and thesecond portion are arranged in a predetermined pattern relative to oneanother to provide a maximum amount of capacitance per area of asemiconductor die; and connecting a node between the offset capacitorand the non-inverting input of the amplifier to ground to cause thecapacitor to charge to the offset voltage.
 80. A method for correctingoffset voltage in an amplifier, comprising: connecting an output of theamplifier to an inverting input of the amplifier; connecting an offsetcapacitor between the inverting input of the amplifier and thenon-inverting input of the amplifier, wherein the capacitor comprises alayer of conductive material, the layer of conductive material includingat least a first portion and a second portion, wherein the first portionand the second portion are arranged in a predetermined pattern relativeto one another to provide a maximum amount of juxtaposed surface areabetween the first and second portions; and connecting a node between thecapacitor and the non-inverting input of the amplifier to ground tocause the capacitor to charge to the offset voltage.
 81. A method forcorrecting offset voltage in an amplifier, comprising: connecting anoutput of the amplifier to an inverting input of the amplifier;connecting an offset capacitor between the inverting input of theamplifier and the non-inverting input of the amplifier, wherein thecapacitor comprises: a first substantial comb-like structure ofconductive material including a plurality of teeth; and a secondsubstantially comb-like structure of conductive material including aplurality of teeth, wherein the teeth of the second substantiallycomb-like structure are interleaved with the teeth of the firstsubstantially comb-like structure, and wherein each tooth of the firstand second comb-like structures have a pair of sidewalls, each sidewallhaving a selected surface area and each of the teeth of the firstcomb-like structure and the second comb-like structure being separatedby a gap of a chosen width to provide a predetermined capacitance; andconnecting a node between the capacitor and the non-inverting input ofthe amplifier to ground to cause the capacitor to charge to the offsetvoltage.
 82. A method for correcting offset voltage in an amplifier,comprising: connecting an output of the amplifier to an inverting inputof the amplifier; connecting an offset capacitor between the invertinginput of the amplifier and the non-inverting input of the amplifier,wherein connecting the capacitor comprises: forming a firstsubstantially comb-like structure of conductive material including aplurality of teeth; and forming a second substantially comb-likestructure of conductive material including a plurality of teeth, whereineach tooth of the first and second comb-like structures have a pair ofsidewalls with a selected surface area and wherein the first comb-likestructure and the second comb-like structure are interleaved to providea maximum capacitance; and connecting a node between the capacitor andthe non-inverting input of the amplifier to ground to cause thecapacitor to charge to the offset voltage.
 83. A method of applying astable voltage to a column or row line of a memory device, comprising:forming an amplifier connected to the column line or row line; forming acapacitor connected to an input of the amplifier; forming circuitry tocharge the capacitor to an opposite polarity of the offset voltage tonullify the offset voltage of the amplifier, wherein forming thecapacitor comprises: depositing at least one layer of conductivematerial on a substrate; and removing material from the layer ofconductive material to form a first portion and second portion arrangedin a predetermined pattern relative to one another to provide a maximumamount of juxtaposed surface area between the first and second portions.84. A method of applying a stable voltage to a column or row line of amemory device, comprising: forming an amplifier connected to the columnline or row line; forming a capacitor connected to an input of theamplifier; forming circuitry to charge the capacitor to an oppositepolarity of the offset voltage to nullify the offset voltage of theamplifier, wherein forming the capacitor comprises: depositing at leastone layer of conductive material on a substrate; removing material fromthe layer of conductive material to form a first portion and secondportion arranged in a predetermined pattern relative to one another toprovide a maximum amount of capacitance per area of the substrate.
 85. Amethod of applying a stable voltage to a column or row line of a memorydevice, comprising: forming an amplifier connected to the column line orrow line; forming a capacitor connected to an input of the amplifier;and forming circuitry to charge the capacitor to an opposite polarity ofthe offset voltage to nullify the offset voltage of the amplifier,wherein forming the capacitor comprises: depositing at least one layerof conductive material; removing a portion of the at least one layer ofconductive material to form a first substantially comb-like structureincluding a plurality of teeth; and removing another portion of the atleast one layer of conductive material to form a second substantiallycomb-like structure including a plurality of teeth, wherein the teeth ofthe second substantially comb-like structure are interleaved with theteeth of the first substantially comb-like structure, and wherein eachtooth of the first and second comb-like structures have a pair ofsidewalls, each sidewall having a selected surface area and each of theteeth of the first comb-like structure and the second comb-likestructure being separated by a gap of a chosen width to provide apredetermined capacitance.
 86. A method of applying a stable voltage toa column or row line of a memory device, comprising: connecting anamplifier to the column line or row line; connecting a capacitor to aninput of the amplifier; forming circuitry to charge the capacitor to anopposite polarity of the offset voltage to nullify the offset voltage ofthe amplifier, wherein the capacitor comprises: a first substantialcomb-like structure of conductive material including a plurality ofteeth; and a second substantially comb-like structure of conductivematerial including a plurality of teeth, wherein the teeth of the secondsubstantially comb-like structure are interleaved with the teeth of thefirst substantially comb-like structure, and wherein each tooth of thefirst and second comb-like structures have a pair of sidewalls, eachsidewall having a selected surface area and each of the teeth of thefirst comb-like structure and the second comb-like structure beingseparated by a gap of a chosen width to provide a predeterminedcapacitance.
 87. A method for correcting offset voltage in an amplifier,comprising: connecting an output of the amplifier to an inverting inputof the amplifier; connecting an offset capacitor between the invertinginput of the amplifier and a non-inverting input of the amplifier,wherein the capacitor comprises a layer of conductive material includingat least a first portion and a second portion and a layer of insulationmaterial disposed at least between the first portion and the secondportion, wherein the first portion and the second portion are arrangedin a predetermined pattern relative to one another to provide a maximumamount of capacitance per area of a semiconductor die; and connecting anode between the offset capacitor and the non-inverting input of theamplifier to ground to cause the capacitor to charge to the offsetvoltage.
 88. The method of claim 87, wherein the predetermined patternincludes a substantially comb-like structure wherein teeth of the firstportion are interleaved with teeth of the second portion.
 89. The methodof claim 87, wherein the predetermined pattern is a substantiallycomb-like structure wherein teeth of the first portion and teeth of thesecond portion are interleaved.
 90. A method for correcting offsetvoltage in an amplifier, comprising: connecting an output of theamplifier to an inverting input of the amplifier; connecting an offsetcapacitor between the inverting input of the amplifier and anon-inverting input of the amplifier, wherein the capacitor comprises alayer of conductive material including at least a first portion and asecond portion, wherein the first portion and the second portion arearranged in a predetermined, substantially serpentine pattern relativeto one another to provide a maximum amount of capacitance per area of asemiconductor die; and connecting a node between the offset capacitorand the non-inverting input of the amplifier to ground to cause thecapacitor to charge to the offset voltage.
 91. A method for connectingoffset voltage in an amplifier, comprising: applying a first timingsignal that connects an output of the amplifier to a first input of theamplifier, connects a first plate of an offset capacitor to the firstinput, connects a second plate of the offset capacitor to a second inputof the amplifier and ground; delaying for a predetermined delay; afterthe predetermined delay, disconnecting the output of the amplifier fromthe first input, disconnecting the first plate from the first input, anddisconnecting the second plate from ground; and applying a second timingsignal to connect input signal to the amplifier.
 92. The method of claim91, wherein delaying for the predetermined time includes charging theoffset capacitor to the value of the offset voltage with an oppositepolarity.
 93. The method of claim 91, wherein applying the first signalincludes connecting a substantially comb-like first plate of the offsetcapacitor to the first input, and connecting a substantially comb-likesecond plate of the offset capacitor to the second input and ground. 94.The method of claim 93, wherein connecting the substantially comb-likefirst plate and connecting a substantially comb-like second plateinclude arranging the first plate and the second plate in apredetermined pattern relative to one another to provide a maximumamount of capacitance per area of a semiconductor die.
 95. The method ofclaim 93, wherein connecting the substantially comb-like first plate andconnecting a substantially comb-like second plate include arranging thefirst plate and the second plate in a predetermined pattern relative toone another to provide a maximum amount of juxtaposed surface areabetween the first plate and the second plate.
 96. A method forcorrecting an offset voltage in an amplifier on a semiconductor die,comprising: connecting an output of the amplifier to a first switch;connecting an inverting input of the amplifier to the first switch;connecting a second switch to the inverting input; connecting a thirdswitch to the non-inverting input of the amplifier and ground;connecting an offset capacitor, which includes a first portion and asecond portion arranged in a pattern to maximize capacitance persemiconductor die area, between the second switch and the non-invertinginput; disconnecting the inverting input and non-inverting input from aninput signal; and closing the first, second, and third switches tocharge the capacitor to the offset voltage.
 97. The method of claim 96,wherein disconnecting the inverting input and the non-inverting inputinclude opening input switches between an input signal and the invertinginput and the capacitor.
 98. The method of claim 96, wherein closing thefirst, second, and third switches includes holding the first, second,and third switches closed for a time period sufficient to fully chargethe capacitor.
 99. The method of claim 96, wherein closing the first,second, and third switches includes opening the first, second, and thirdswitches after a time delay and applying an input signal to theinverting input and the capacitor to produce an output from theamplifier that is independent of frequency and the amplifier offsetvoltage.
 100. The method of claim 99, wherein applying the input signalincludes applying a magnetic random access memory signal to theinverting input and the capacitor.
 101. The method of claim 100, whereinapplying the magnetic random access memory signal includes applying asignal to drive column lines of a magnetic random access memory device.102. A method, comprising: providing an input circuit, which has anoffset voltage, to a memory device; providing a memory connected to theinput circuit; correcting the offset voltage of the input circuit,wherein correcting the offset voltage includes: connecting an output ofan amplifier of the input circuit to an inverting input of theamplifier; connecting the inverting terminal to an offset capacitor;connecting the offset capacitor to a non-inverting input of theamplifier; connecting the non-inverting input to ground; charging theoffset capacitor to the offset voltage; after a time period,disconnecting the output from the inverting input; after the timeperiod, disconnecting the inverting input from the offset capacitor;after the time period, disconnecting the non-inverting input fromground; applying an input signal to the non-inverting input and theoffset capacitor; and outputting a signal from the output to the memory.103. The method of claim 102, wherein outputting the signal includesoutputting a signal corrected for the offset voltage of the amplifierand independent of the frequency of the input signal.
 104. The method ofclaim 102, wherein applying the input signal includes applying acolumn-line control signal to the amplifier.
 105. The method of claim104, wherein outputting the signal includes outputting a column-linedrive signal from the output of the amplifier.
 106. The method of claim105, wherein outputting the column-line drive signal includes outputtingthe column-line drive signal to a magnetic random access memory (MRAM).107. The method of claim 106, wherein outputting the column-line drivesignal includes outputting the column-line signal to a multiplexor whichis connected to a plurality of column lines.
 108. The method of claim102, wherein charging the capacitor includes charging a first portionthat has a first plurality of teeth and grounding a second portion thathas a second plurality of teeth interleaved with the first plurality ofteeth to provide a maximum amount of juxtaposed surface area between thefirst and second portions.